This letter proposes a new shaping algorithm (CRSA: CDV Reduction Shaping Algorithm) that can freely reduce the maximum CDV value of a cell stream to any predetermined value. There is a trade off between shaping delay and the maximum CDV value reduction achieved when using CRSA. The shaper using CRSA (CR-shaper) output satisfies the Peak Cell Rate Reference Algorithm set with the CR-shaper parameters.

This paper shows that a network supplying variable bit rate services can be prevented from becoming congested if each terminal limits the capacity of its connection in terms of its rate of increase. Variable bit rate sources are adequately assessed with two new concepts: the bit rate increase per unit time (acceleration-rate=αbit/sec2) or the bit rate increase ratio (acceleration-ratio=exp (β) ). The dimension of the acceleration-ratio coefficient βis seconds-1. The upper limits α and β are regulated to guarantee the network's QoS. The proposed concepts allow the network state to be accurately estimated and avoid congestion. The proposed method can be applied to ATM networks, Frame Relay networks, Fast Reservation Protocol systems and so on.

A new high-performance fault-tolerant ATM switching network is proposed. This network contains the baseline network and has many redundant switching elements to enhance the fault tolerance and throughput of the conventional multistage interconnection networks. The presented routing algorithm is very simple and can support a very huge number of paths between each input-output pair. The paths can be used to route cells when internal cell contentions occur in switching elements. The redundant switching elements at the last stage offer two access points to the output ports to resolve the output conflict. Performance analysis and simulation results show that this network has better maximum throughput even for faulty conditions. Among various networks, it has the largest number of redundant paths, and the greatest unit node contribution and unit edge contribution.

For a CBR (Constant Bit Rate) connection in an ATM (Asynchronous Transfer Mode) network, we determine the CDV (Cell Delay Variation) tolerance for the mapping of ATM cells from the ATM Layer onto the Physical Layer. Our result will be useful to properly allocate resources to connections and to accurately enforce the contract governing the user's cell traffic by UPC (Usage Parameter Control).

A local area network (LAN) can now provide high-speed data communications in a local area environment to establish distributed processing among personal computers and workstations, and the need for interconnecting LANs, which are geographically distributed, is naturally arising. Asynchronous Transfer Mode (ATM) technology has been widely recognized as a promising way to provide the high-speed wide area networks (WAN) for Broadband Integrated Services Digital Network (B-ISDN), and the commercial service offerings are expected in the near future. The ATM network seems to have a capability as a backbone network for interconnecting LANs, and the LAN interconnection is expected to be the first service in ATM networks. However, there remain some technical challenges for this purpose; one of the main difficulties in LAN interconnection is the support of connectionless traffic by the ATM network, which is basically a connection-oriented network. Another one is the way of achieving the very high-speed data transmission over the ATM network. In this paper, we first discuss a LAN internetworking methodology based on the current technology. Then, the recent deployments of LAN interconnection methods through B-ISDN are reviewed.

This paper deals with methods for interconnection between two local private networks that are geographically separated. A scheme is first presented to chain low bit-rate physical circuits into one logical circuit, over which ATM cells are transmitted as if there is one circuit with a high bit-rate capacity. In particular, use of existing low bit-rate circuits, e.g., 384/1536 kbit/s PDH leased line services and N-ISDN switched channels, is considered. The paper discusses two methods to permit chaining of physical circuits, and identifies their advantages and applications. By using the ATM-based circuit-chaining method, dynamic capacity control of the interconnection is then introduced with the use of an ATM-based rate adaptation. This is intended to provide a flexible and cost-effective capacity control compared to the existing TDM-based control. It is also possible to realize non-stop operation of changing capacity by establishment and release of chained circuits, which will lead to high reliability and robustness of private networks. Finally, delay characteristics introduced by the method are evaluated based on a computer simulation which gives a short and acceptable delay.

Asynchronous Transfer Mode (ATM) shared buffer switches have numerous advantages, but have the principal disadvantage that all switch traffic must pass through the bottleneck of a single memory. To achieve the most efficient usage of this bottleneck, the shared buffer is made blockable, resulting in a switch architecture that we call "throttled-buffer", which has several advantageous properties. Shared buffer efficiency is maximized while decreasing both capacity and power requirements. Asynchronous operation is possible, whereby peak link data rates are allowed to approach the aggregate switch rate. Multicasting is also efficiently supported. The architecture and operation of this low-cost switch are described in detail.

A circuit emulation technique in the ATM network becomes necessary to guarantee user requirements similar to QOS grade offered by STM network where small bit error rates and constant delay times are offered. The Head-Of-Line method or other priority control schemes may be considered to provide such service in the ATM network, while it is known to give too inferior quality to non-circuit emulation service traffic. In this paper, we propose a new method called a periodical bandwidth allocation method for the circuit emulation technique. The cells of circuit emulation service traffic are transmitted periodically in our proposal. A periodical interval is determined from both the length of limit delay time of circuit emulation traffic in each switching node and the number of cell arrivals during the limit delay time. To evaluate our method, we consider three kinds of arrival patterns (the best case, the moderate case, and the worst case) for the circuit emulation traffic and a two-state MMPP for modeling the non-circuit emulation traffic. We show performance results in terms of the cell loss probability and the mean delay time in our proposal through analytic and simulation approaches.